1. Field of the Invention
The present invention relates to a semiconductor memory device having a sense amplifier for amplifying data stored in a memory cell, and particularly relates to a semiconductor memory device configured to pre-charge a power supply line pair for supplying power to the sense amplifier.
2. Description of the Related Art
Generally, a DRAM as a semiconductor memory device has a configuration in which a large number of memory cells are arranged at intersections of a plurality of bit lines and a plurality of word lines. A cross failure due to a short circuit between a word line and a bit line is know as one of defects which cause trouble in manufacturing the DRAM. In order to cope with an increase in current due to the cross failure, the DRAM is generally configured to have redundant cells, and a defective cell corresponding to a word line and a bit line at which the cross failure exists is replaced with a redundant cell. Although operational trouble in the DRAM can be prevented by employing such measures, current leak due to the cross failure is a problem since specification for current in the DRAM for mobile use which requires low power consumption is strict. That is, a current leak path via a circuit portion including the cross failure in the DRAM remains regardless of the redundant cells, and therefore depending on the number of cross failures, products may become defective which does not satisfy the specification for current. Thus, an increase in the number of cross failures causes a decrease in manufacturing yield. In order to take measures against such a problem, a configuration in which a current limiter for limiting current flowing in a bit line equalize circuit is employed (refer to, e.g., Japanese Patent Application Publication No. H11-149793).
FIG. 12 is an example of the configuration of the conventional DRAM including the above-mentioned current limiter, in which an area including one word line WL and two pairs of the bit lines BL and bBL are shown. In FIG. 12, a circuit portion corresponding to a bit line pair BL(i) and bBL(i) where the cross failure does not exist, and a circuit portion corresponding to a bit line pair BL(j) and bBL(j) where the cross failure CF exist are compared. A sense amplifier SA connected to the respective bit line pair BL and bBL is provided to amplify a minute potential difference of each memory cell MC, and a power supply line SAP on the PMOS transistor side and a power supply line SAN on the NMOS transistor side are connected thereto. There are provided a bit line equalize circuit 301 for pre-charging/equalizing the bit line pair BL and bBL based on an equalize control line EQD of the bit line side, and a current limiter 302 inserted between a pre-charge power supply line VHVD and the bit line equalize circuit 301. Further, there are provided a sense amplifier drive circuit 303 for driving the sense amplifier SA, and a power supply line equalize circuit 304 for pre-charging/equalizing a power supply line pair SAP and SAN based on an equalize control line EQ of the power line side.
Operation of the DRAM of FIG. 12 in a self refresh period will be described with reference to a timing chart of FIG. 13. First, a pulse of a trigger signal TRG representing the start of the self refresh operation is output from a control logic unit (not shown). At this point, the equalize control lines EQ and EQD are maintained high, and the bit line pair BL and bBL and the power supply line pair SAP and SAN are pre-charged. Thereafter, the equalize control lines EQ and EQD change to low to finish the pre-charge, the word line WL rises to a selection level to start the self refresh operation, and large potentials appear on the bit line pair BL and bBL and the power supply line pair SAP and SAN. When the self refresh is finished, the word line WL falls and the equalize control lines EQ and EQD change to high. Thereby, the bit line pair BL and bBL and the power supply line pair SAP and SAN are pre-charged again. At this point, the level of the bit line pair BL(j) and bBL(j) where the cross failure CF exists gradually decreases to near the ground level due to discharge caused by current leak while keeping the same potential as each other. In this case, current flowing from the pre-charge power supply line VHVD through the bit line equalize circuit 301 is limited by the current limiter 302.
However, lower voltage is required for recent DRAMs for mobile use, a threshold voltage Vt of a PMOS transistor in the sense amplifier SA is decreased, a problem of current leak which is different from the conventional DRAM arises. That is, in the configuration of FIG. 12, there is a current leak path P from the pre-charge power supply line VHVD through the power supply line equalize circuit 304, the power supply line SAP, a pair of PMOS transistors of the sense amplifier SA, the bit line pair BL(j) and bBL(j), the bit line equalize circuit 301, the cross failure CF and the word line WL. This is because if a negative potential is supplied to the word line WL due to the lower voltage of the DRAM, the potential of the bit line BL(j) is decreased due to the cross failure CF, and thereby the PMOS transistors of the sense amplifier SA tend to be on. Accordingly, particularly in the self refresh period of the DRAM, the influence of the current leak flowing through the current leak path P including the power supply line pair SAP and SAN is inevitable. Even if the measures are taken by using the above-mentioned current limiter 302, since consumption current is remarkably increased due to the current leak path P, a problem arises in that an increase in consumption current and a decrease in manufacturing yield caused by an increase in cross failures CF cannot be suppressed.